SidekiqX4

A high bandwidth, multi-channel RF transceiver for advanced RF solutions

Sidekiq X4

Maximize Your RF Bandwidth

with an increased number of phase coherent channels

The Sidekiq X4 multi-channel RF transceiver card introduces a new level of RF integration and capability, speeding product development cycles and improving wideband range versatility and performance. The Sidekiq X4 integrates two  Analog Devices’ ADRV9009 wideband transceivers,  creating a very flexible and high capacity RF transceiver solution that resides in VITA 57.1 FPGA Mezzanine Card (FMC) form factor. Sidekiq X4 includes multi-band, sub-octave,  filtering  on four receive paths.

Up to 800 MHz Instantaneous BW

Up to 4 phase-coherent channels

VITA57.1 FMC (3U VPX compatible)

Flexible RF Front End

Sidekiq X4 integrates two Analog Devices ADRv9009 wideband transceivers, providing 4 receivers and 4 transmitters. The receivers can be phase coherent or independently tunable, while the transmitters can all be phase coherent or split into two phase coherent pairs. Each channel's bandwidth is configurable up to 200 MHz, with special modes to support up to 400 MHz per channel, for a total IBW of 800 MHz.

Key Features

X4 offers best-in-industry integration and overall capabilities

  • RF Tuning Range

    1 MHz to 6 GHz

  • A/D Sample Width

    16 bits

  • Form Factor

    VITA57.1 High Pin Count FPGA Mezzanine Card

  • D/A Sample Width

    14 bits

  • Rx Noise Figure

    8 dB (typ.)

  • Channel Bandwidth

    Up to 200 MHz (see spec sheet for more info)

  • Tx Output

    Up to +5 dB

  • Power Consumption

    7 - 14 Watts

  • Max A/D Sample Rate

    245.76 Msamples/sec

Ready for Development

Sidekiq X4 supports lab and field deployments with a COTS PCIe-based FPGA carrier card and a GPS disciplined oscillator card integrated into a ThunderboltTM 3 chassis or COTS 3U and 6U VPX carrier cards for ruggedized deployments. The Sidekiq X4 Platform Development Kit (PDK) provides customers with access to both a software API for interfacing to the card, as well as the source code for the FPGA reference design.

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